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64-bit processors: Intel 64 – NetBurst microarchitecture. Intel Extended Memory 64 Technology; Mostly compatible with AMD's AMD64 architecture; Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings) Pentium 4F. Prescott-2M built on 0.09 μm process technology; 2.8–3.8 GHz (model numbers 6x0) Introduced February 20, 2005
Chipset. Intel 910GML, 915GMS, 915GM, 915GME, 910GMLE, and 915PM Express mobile chipsets, for use with the Celeron M and Pentium M (Banias, Dothan) processors. Alviso, a small neighborhood in San Jose, California, the closest San Jose neighborhood to Intel's Santa Clara headquarters. 2004.
Rocket Lake is Intel 's codename for its 11th generation Core microprocessors. Released on March 30, 2021, [2] it is based on the new Cypress Cove microarchitecture, a variant of Sunny Cove (used by Intel's Ice Lake mobile processors) backported to Intel's 14 nm process node. [4] Rocket Lake cores contain significantly more transistors than ...
Cairo — Microsoft Windows NT 4.0. Calais — Sun Next generation JavaStation. Calexico — Intel PRO/Wireless 2100B. Calistoga — Intel chipsets for Napa platforms. Calvin — Sun SPARCStation 2. Camaro — AMD Mobile Duron. Cambridge — Fedora Linux 10. Camelot — Sun product family name for Arthur, Excalibur, Morgan.
The latest badge promoting the Intel Core branding. The following is a list of Intel Core processors. This includes the original Core (Solo/Duo) mobile series based on the Enhanced Pentium M microarchitecture, as well as Core 2 (Solo/Duo/Quad/Extreme), Core i3, Core i5, Core i7, Core i9, Core M (m3/m5/m7), Core 3, Core 5 and Core 7 branded processors.
Max. CPU clock rate. Tiger Lake is Intel's codename for the 11th generation Intel Core mobile processors based on the Willow Cove Core microarchitecture, manufactured using Intel's third-generation 10 nm process node known as 10SF ("10 nm SuperFin"). Tiger Lake replaces the Ice Lake family of mobile processors, [4] representing an optimization ...
released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2 . Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
Processor Code name Device id. Core clock Execution units API support Memory bandwidth DVMT QSV; Direct3D OpenGL OpenCL; HD Graphics 2011 Mobile Celeron B7x0 Celeron 7x7 Celeron 8x7 Celeron B8xx Pentium B9x0 Pentium 9x7 Sandy Bridge: 010A 350–1150 6 (GT1) 10.1 11.1 Windows 8+ FL10_1 3.1 Windows 3.3 macOS 3.3 Linux ES 3.0 Linux: No 21.3 1720 ...
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